The present invention relates to low-profile semiconductor devices which can be packaged with high density and a semiconductor module using them, and more particularly to a semiconductor device which can improve heat-cycle resistant characteristic and effectively prevent short-circuiting between solder bumps for packaging and a semiconductor module using them.
Previously known semiconductor modules include SIMMs (Single Memory Module) and DIMMs (Dual Inline Module). The SIMM is a storage module in which a plurality of plastic package ICs are mounted on a single surface of a glass-epoxy substrate, and each of the plastic packaged ICs has an external lead protruding from the side of an IC package body resin-sealed in an epoxy resin. The DIMM is a storage module in which a plurality of the same plastic packaged ICs are mounted on both surfaces of the glass epoxy substrate.
FIG. 13 is a plan view of a conventional semiconductor device, and FIG. 14 is a side view of FIG. 13. In FIGS. 13 and 14, reference numeral 1 denotes a substrate including substrates 1a, 1b, and 1c which are spaced apart from one another. Each substrate component has lands 3 for mounting an IC package 7 on both upper and lower surfaces. The substrate component has also lands 4 outside the lands 3. The lands 4 serve as terminals for external connection. The corresponding lands 3 and 4 are electrically connected to each other by wirings 5 on both surfaces of the substrate 1. The lands 4 for external connection on both surfaces of the substrate 1 are connected to each other by conductors embedded in through-holes.
A solder bump 6, located at the tip of the land 4 for making an external connection on the one surface of the substrate 1 (lower side in FIG. 14). The IC package 7 includes a package body 8 and straight leads 9 which protrude laterally from both right and left sides of the body 8. The straight leads 9 are electrically connected to the corresponding lands 3 for mounting and supported by the substrate 1. Reference numeral 2 denotes a gap between the substrate 1 (1a, 1b, 1c) and the package body 8. In this way, a semiconductor device 24 includes the substrate 1, lands 3 for mounting, lands 4 for external connection, wirings 5, solder bumps 6 and IC package 7.
The semiconductor device 24 can be manufactured as follows. First, with the IC package 7 positioned on the upper surface of the substrate 1, the straight leads 9 are soldered to the lands 3 for mounting by a re-flow technique. Next, the substrate 1 is turned upside down. Likewise, on the lower surface of the substrate 1, the straight leads 9 of another IC package 7 are soldered to the lands 3 for mounting, and the solder bumps 6 are soldered to the tips of the land 4 for external connection.
The structure of a semiconductor module will be explained. FIG. 15 is a side view of the structure of a conventional semiconductor module in which a plurality of semiconductor devices one of which is shown in FIGS. 13 and 14, are soldered on a mother board 20. As seen from FIG. 15, lands 21 for mounting the semiconductor device 24 are formed on the upper surface of the mother board 20. The solder bumps 6 are electrically connected to the semiconductor device 24, respectively. Likewise, the solder bumps 6 of another semiconductor device 24 are electrically connected to the lands 21 on the lower surface of the mother board 20. In this way, a semiconductor module 25 includes the mother board 20, upper and lower lands 21 and semiconductor devices 24.
The semiconductor module 25 can be manufactured as follows. First, a semiconductor device 24 is positioned on the upper side of the mother board 20. In this case, solder paste is previously supplied to contact positions between the solder bumps 6 and the lands 21. The solder paste and solder bumps 6 are melted and bonded to the lands 21 so that the semiconductor device 24 is secured to the mother board 24. Next, the mother board 20 is turned upside down. Likewise, another semiconductor device 24 positioned on the lower side of the mother board 20 is secured to the mother board 20. Thus, the semiconductor module 25 is completed.
The upper semiconductor device 24 which is first soldered and secured to the mother board 20 and is shown at the lower position in FIG. 15 is caused to xe2x80x9creflowxe2x80x9d in its dangling state. Therefore, the solder bumps 6 are extended downward owing to the weight of the semiconductor device itself so that they are deformed in a xe2x80x9ctsuzumixe2x80x9d (hand drum) shape with its diameter decreasing toward center. On the other hand, the upper semiconductor device 24 which is afterward, soldered and secured to the mother board 20 and is shown at the upper position in FIG. 15 is caused to reflow in a state placed on the mother board 20. Therefore, the solder bumps 6 are compressed owing to the weight of the semiconductor device itself so that they become deformed in a barrel shape with its diameter increasing toward center. FIG. 16 is a schematic side view of the solder bumps 6 thus deformed on the upper and lower surfaces of the semiconductor module 25. If the upper solder bumps are crushed as seen from FIG. 16 so that they are going to swell in diameter from the prescribed positions together with the paste, the solder bumps 6 may be short-circuited to each other at the time of reflow, provided that the bonding pitch between the adjacent solder bumps 6 is small.
The lower solder bump 6, as seen from FIG. 16, becomes deformed into the xe2x80x9ctsuzumixe2x80x9d shape during its reflow so that the sectional area of the bonding portion is going to decrease. Therefore, when the completed semiconductor module 25 is subjected to the temperature cycle test in which a temperature change from xe2x88x9240xc2x0 C. to 125xc2x0 C. is made every thirty minutes, the soldered portion may be broken owing to a crack due to thermal fatigue. The breakage due to the thermal fatigue is likely to occur at the region where the maximum bending moment due to thermal deformation is applied to the bonding end of the solder bump, i.e. the bonding boundary between the land 4 for external connection having a small sectional area and the solder bump 6. However, the usable solder bump 6 must have a small diameter under the limitation of the pitch between the adjacent leads. Therefore, breakage may occur at the portion having a small secondary moment at the sectional area of the bonding boundary, i.e., having a small sectional area at the bonding boundary.
On the other hand, the semiconductor module 25 incorporates the mother boards 20 having different thermal expansion coefficients, substrates 1, IC packages 7 and circuit components (not shown).
Therefore, thermal deformation occur at the soldering portion owing to a temperature change during the operation or during the temperature cycle test. The quantity of the thermal deformation is proportional to the difference between the different thermal expansion coefficients, distance and temperature difference between the soldering portions. The largest thermal deformation occurs at the soldering portions of the lands 4 for external connection corresponding to the lands 3 for mounting at both ends which are secured by soldering and interpose the longest distance therebetween. The breakage may occur at the soldering portions of these both ends.
The holding strength with N solder bumps 6 aligned in a row on both sides of the IC package 7, when the IC package 7 is bonded to the substrate 1 can be represented as follows. In this case, the solder bump 6 is approximated as a cylinder having a diameter D. Assuming that the permissible stress of solder at the temperature of reflow, e.g., about 200xc2x0 C. is "sgr"a and the permissible holding weight of the entire solder cylinder of the solder bump 6 is Wa, Wa="sgr"axc3x97xcfx80xc3x97Dxc3x97Dxc3x972xc3x97N/4. From this equation, it can be seen that the permissible holding weight of the solder bump 6 can be increased by increasing the diameter D of the solder bump 6 and the number N of the solder bumps 6.
However, increasing the diameter of the solder bump 6 and the number of the solder bumps 6 presents the following problem. Namely, on the substrate 1, the lands 3 for mounting are aligned densely in a row with a pitch P1 in order to bond the straight leads 9 protruding from both sides of the IC package 7. Therefore, the lands 4 for external connection must be provided outside the lands 3 for mounting. This correspondingly increases the width of the substrate, thereby increasing the mounting area. In order to align the N soldering bumps 6 in a row at the pitch P1 on the substrate 1, the size of (Nxe2x88x921)xc3x97P1 is required in the aligned direction. It can be seen from this equation that in order to decrease the size of the substrate 1 and increase the number of the solder bumps 6, it is necessary to decrease the pitch P1.
Assuming that the distance between the solder bumps 6 is W, the diameter D=P1xe2x88x92W. In order to increase the diameter D of the solder bump 6, the pitch P1 between-the adjacent solder bumps 6 must be increased. This means that the pitch of the straight leads 9 (or wirings 5) must be increased. However, the conventional semiconductor device 24 cannot simultaneously satisfy the contradictory requirements of increasing the diameter of the solder bump 6 and increasing the number N of the solder bumps 6 to decrease its pitch. Thus, there is a limitation in mounting the IC package having multiple pins and narrow pitch.
In order to bond the straight leads 9 of the package body 8 to the substrate 1, the lands 3 for mounting must be provided in a row substantially parallel to the side of the package body 8. Therefore, the lands 4 for external connection cannot be provided on the areas where the lands 3 are provided. The lands 4 for external connection must be inevitably provided outside the lands 3 for mounting. This correspondingly increases the mounting area of the semiconductor device 24 and the semiconductor module 25 and hence cannot downsize them.
The thickness of the sealing resin for the package body 8 mounted on the substrate 1 so as to constitute the semiconductor device 24 is at most 1 mm, even in the most low-profile IC package 7. The thickness of the straight leads 9 for external extension is 0.125 mm. Therefore, the thickness (H in FIG. 14) of the sealing resin from the surface of the straight lead 9 to the outer surface of the package body 8 is H=((1xe2x88x920.125)/2)+0.125=0.5625 mm. In order to bond the semiconductor device 24 to the mother board 20 with no hitch, assuming that the thickness of the solder paste for bonding the solder bumps is 65 xcexcm, the requirement D+2xc3x970.065 mm  greater than 0.5625 mm, i.e., the diameter of the solder bump 6 greater than 0.435 mm, must be satisfied. If not so, the package body 8 and the mother board 20 are brought into contact with each other so that the solder bump 6 cannot be bonded to the land 21 and hence the semiconductor module 25 cannot be constructed. Now if the solder bumps 6 each having the diameter D of 0.45 mm and distance of 0.35 mm between the adjacent bumps are used, the IC package 7 can be mounted with the lead pitch P1=0.45+0.35=0.8 mm.
Now, when it is intended that the IC package 7 be mounted with a smaller lead pitch (P1=0.65 mm, 0.5 mm and 0.4 mm) using the solder bumps 6 each having a diameter of 0.45 mm, in the case of the IC package 7 with P1=0.65 mm, the gap W between the adjacent solder bumps 6 is W=0.65xe2x88x920.45=0.2 mm. In this case, after the soldering paste has been solder-printed on the substrate 1 and mother board 20, when the solder bumps 6 are bonded by its reflow, the molten solder paste flows into the small gap of W=0.2 mm between the solder bumps 6 so that the solder bumps may be short-circuited to each other. In this way, in the conventional technique, since the ball interval between the adjacent solder bumps 6 for external connection depends on the lead pitch of the straight leads 9 of the IC package 7. This presents the problem that the semiconductor module 25 including the IC packages 7 each having the standard of the smaller lead pitch P1=0.65 mm, 0.5 mm, 0.4 mm cannot be constructed.
Further, the lands 3 for mounting to be connected to the straight leads 9 of the semiconductor device 24 are aligned with equal pitches P1 in a row. The corresponding lands 4 for external connection are aligned with equal pitches in a row outside the lands 3 for mounting. Therefore, the region bonded by solder or solder bump 6 provided an equivalent thermal expansion coefficient and equivalent vertical elastic coefficient that are different from those between the straight leads 9 and substrate 1 and between the substrate and the mother board 20, and hence the thermal stress may be increased.
An object of the present invention is to provide a low-profile highly-productive semiconductor device that does not raise short-circuiting between adjacent solder bumps and provides high bonding strength of the solder bonding area in a configuration in which the solder bumps for external connection each has a larger diameter than the distance-from the lands for external connection of a substrate to the outer surface of an IC package having external electrodes with a small lead pitch mounted on the substrate.
Another object of the invention is to reduce the thermal stress of the region of bonding a solder bump.
Still another object of the invention is to improve the standardization of the diameter of the solder bump and its productivity.
A semiconductor device according to the invention comprises:
an IC package having a plurality of external electrodes exposed to the rear surface of a package body; and
a substrate provided with lands for mounting to which the external electrodes are bonded, lands for external connection connected to solder bumps for external connection and formed outside an area where the IC package is mounted, and wirings for connecting the lands for mounting and the lands for external connection.
In the semiconductor device according to the invention, the lands for mounting, the lands for external connection and the wirings are formed on an upper surface and a lower surface of the substrate; the corresponding lands for external connection on both surfaces are electrically connected to each other and the solder bumps are connected to the lands for external connection on the one surface; and the external electrodes are connected to at least one of the lands for mounting on both surfaces of the substrate.
In the semiconductor device according to the invention, the IC package is a BOC package, and the substrate includes a through-hole for receiving potting resin, the potting resin sealing a wire bonding portion of the BOC package to protrude when the BOC package is mounted on the substrate.
In the semiconductor device according to the invention, the lands for external connection includes a first group of lands for external connection which are arranged with pitches twice as long as those of the wirings on both sides of the package body; and a second group of lands for external connection which are arranged with pitches twice as long as those of the wirings outside the first group of lands for external connection, the second group of lands for external connection being arranged in a displaced manner from the first group of lands for external connection in their column directions.
In the semiconductor device according to the invention, dummy lands for external connection which are not connected to the external electrodes of the IC package are formed outside the ends of columns of the first group of lands for external connection and second group of lands for external connection which are formed on the upper and lower surface of the substrate, and the solder bumps are bonded to the dummy lands for external connection which are formed on the same plane as that of the lands for external connection to which the solder bumps are bonded.
The semiconductor module comprises the semiconductor device defined in any one of the above invention; and a mother board of which on the upper and lower surfaces, lands are formed for mounting semiconductor device, and solder bumps are bonded to the lands.
In the semiconductor module according to the invention, the lands for external connection and the lands to which the solder bumps are bonded, respectively have equal diameters.
In the semiconductor module according to the invention, the solder bumps bonded to the first group of lands for external connection on the one side of a first semiconductor device are arranged on an upper surface of the mother board, and the solder bumps bonded to the second group of lands for external connection on the one side of a second semiconductor device are arranged on the lower surface of the mother board on the same side as the one side of the first semiconductor device;
and the solder bumps bonded to the second group of lands for external connection are arranged on the other side of the first semiconductor device on the upper surface of the mother board, and the solder bumps bonded to the first group of lands for external connection on the other side of the second semiconductor device are arranged on the lower surface of the mother board on the same side as the other side of the first semiconductor device.
The semiconductor module including the semiconductor device defined in the invention comprises a mother board of which on the upper and lower surfaces, lands are formed for mounting semiconductor device, and solder bumps are bonded to the lands.
In the semiconductor module according to the invention, the lands for external connection, dummy lands for external connection and the lands to which the solder bumps are bonded, respectively have equal diameters.
In the semiconductor module according to the invention, the solder bumps bonded to the first group of lands for external connection and dummy lands for external connection on same columns as them on the one side of a first semiconductor device are arranged on an upper surface of the mother board, and the solder bumps bonded to the second group of lands for external connection and dummy lands for external connection on the same columns as them on the one side of a second semiconductor device are arranged on the lower surface of the mother board on the same side as the one side of the first semiconductor device; and the solder bumps bonded to the second group of lands for external connection and dummy lands for external connection on the same column as them are arranged on the other side of the first semiconductor device on the upper surface of the mother board, and the solder bumps bonded to the first group of lands for external connection and dummy lands for external connection on the same columns as them on the other side of the second semiconductor device are arranged on the lower surface of the mother board on the same side as the other side of the first semiconductor device.